1. Field of the Invention
The present invention relates to the physical arrangement of signal lines transmitting signals between devices, and particularly relates to the physical arrangement of a plurality of signal buses each including a plurality of signal lines. More specifically, the present invention relates to a bus arrangement for reducing cross-talk noise between signal lines.
2. Description of the Background Art
FIG. 10 shows an example of the constitution of a conventional processing system. In FIG. 10, the processing system includes a processor PC and memory units MDA to MDN coupled to processor PC through buses BUSA to BUSN, respectively. Each of buses BUSA to BUSN includes an address bus transmitting address signals, a control bus transmitting control signals and a data bus transmitting data.
FIG. 11 is a timing chart representing an operation of the processing system shown in FIG. 10. In an operation sequence shown in FIG. 11, data is transmitted between processor PC and memory units MDA to MDN synchronously with a master clock signal CLK in this processing system.
As shown in FIG. 11, processor PC accesses memory units MDA to MDN at different timings (or in different clock cycles) synchronously with the clock signal. In FIG. 11, in response to the rises of clock signal CLK, processor PC transmits address signals to memory units MDA to MDN, respectively, and in response to the fall of clock signal CLK, data is read from memory units MDA to MDN accessed by processor PC. Accordingly, by providing individual buses BUSA to BUSN for memory units MDA-MDN, respectively and by sequentially accessing the buses, data is transmitted in a pipeline manner to achieve high-speed data transmission.
Memory units MDA to MDN may be the same in construction or may be different in type.
With bus connection switched in processor PC, processor PC can transfer data to memory units MDA to MDN in a pipeline manner and can process the data internally in a pipeline manner. In addition, during an internal operation of processor PC, processor PC can access memory units MDA to MDN so as to transmit necessary data thereto. It is, therefore, possible to effectively eliminate wait time in memory access to achieve a processing system capable of processing data at high speed.
FIG. 12 shows an example of the construction of a conventional semiconductor integrated circuit device. In FIG. 12, this semiconductor integrated circuit device CHP is a semiconductor memory device formed on a single semiconductor chip. Semiconductor integrated circuit device CHP includes memory mats MAT0 and MAT1 each having a plurality of memory cells. Memory mat MAT0 includes banks A and C while memory mat MAT1 includes banks B and D. Banks A to D can be driven into a selected state (in which a word line is selected) independently of one another.
Further, semiconductor integrated circuit device CHP includes a central control circuit CTL transmitting an internal address signal and a control signal through an internal bus CBS to each of banks A to D in accordance with an external address signal and an external control signal which are not shown, a data input/output circuit IOK0 inputting and outputting data to and from a selected memory cell in banks A and C, and a data input/output circuit IOK1 inputting and outputting data to and from a selected memory cell in banks B and D.
The internal address signal and the internal control signal are transmitted from central control circuit CTL to each bank through the internal bus CBS and each of banks A to D is driven into a selected state in accordance with the transmitted signals. Inputting/outputting of data is executed for one bank in a selected state.
In semiconductor integrated circuit device CHP as stated above, by providing a plurality of banks A to D and interleavingly accessing banks A to D to thereby avoid the overhead in address transfer, it is possible to achieve high-speed data transmission. Further, by driving a bank into a selected state while selecting and accessing another bank, it is possible to reduce overhead in the switching-over of banks or switching-over of pages.
In each of the processing system shown in FIG. 10 and the semiconductor integrated circuit device shown in FIG. 12, signal buses BUSA to BUSN and internal data bus CBS are arranged. Each of these buses BUSA to BUSN and CBS has a width of a plurality of bits. Buses BUSA to BUSN are formed of on-board wirings or printed wirings and internal bus CBS is constituted of on-chip internal interconnection lines.
FIGS. 13A and 13B are schematic diagrams of a conventional bus signal line arrangement. FIG. 13A typically shows a signal bus BUSA including bus lines BUS_A<0:L> of a width of (L+1) bits and signal bus BUSB including bus lines BUS_B<0:M> of a width of (M+1) bits. Drivers DR are provided for driving the signal lines of bus lines BUS_A<0:L> and BUS_B<0:M>, respectively. These drivers DR are normally operated synchronously with clock signal CLK.
FIG. 13B is a schematic diagram of a cross-sectional structure taken along line 13B-13B′ of FIG. 13A. As shown in FIG. 13B, bus lines BUS_A<0:L> and BUS_B<0:M> include signal interconnection lines SGA and SGB, respectively. Signal interconnection lines SGA of bus lines BUS_A<0:L> are arranged to be adjacent one another and signal interconnection lines SGB of bus lines BUS_B<0:L> are arranged to be adjacent one another.
That is, bus lines BUS_A<0:L> and BUS_B<0:M> are arranged collectively in units of buses. Signal interconnection lines SGA and SGB of bus lines BUS_A<0:L> and BUS_B<0:L> are arranged on the same layer (in both an integrated circuit device and a printed circuit board). This facilitates interconnection layout as well as connections to respective signal input/output circuits.
As shown in FIG. 14, however, there exists a parasitic capacitance Cpr between signal interconnection lines SGs and SGt whichever these bus lines are formed on a printed circuit board or a semiconductor substrate. Here, signal lines SGs and SGt may be any of signal interconnection lines SGA and SGB.
The capacitive coupling of parasitic capacitance Cpr causes cross-talk noise between adjacent signal lines. In case of the capacitive coupling between signals changing in opposite directions, the increase of signal propagation delay, the error of a signal logic level and the like disadvantageously occur. In a clock synchronous system operated synchronously with clock signal CLK, in particular, signals on the signal lines of the same bus are changed synchronously with the clock signal and these signals are, therefore, changed substantially at the same timing, so that the cross-talk noise problem becomes more significant.
To reduce the cross-talk noise, it is necessary to widen a bus line pitch to reduce parasitic capacitance Cpr, which disadvantageously increases a bus layout area. Particularly, when the bus line pitch is widened, recent demand for high integration and down-sizing of a system through narrowing a bus line pitch due to miniaturization cannot be satisfied. The cross-talk noise problem derived from the narrowed line pitch as stated above is common to all the bus arrangement on the printed wiring board, that on the semiconductor integrated circuit device and others.
Further, the above-stated system is not limited to a processing system including a processor and memory units. Even a system having a plurality of processors is encountered with the above-stated cross-talk noise problem if a plurality of individual and separate signal buses are arranged in the system.